Freescale Semiconductor
Technical Data
Document Number: MPC8548EEC
Rev. 10, 06/2014
MPC8548E PowerQUICC III
Integrated Processor
Hardware Specifications
1
Overview
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Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 10
Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 15
Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 19
DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 20
DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Enhanced Three-Speed Ethernet (eTSEC) . . . . . . . . 27
Ethernet Management Interface Electrical
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Programmable Interrupt Controller . . . . . . . . . . . . . 53
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
I
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
GPOUT/GPIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
PCI/PCI-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 65
PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Serial RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 91
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
System Design Information . . . . . . . . . . . . . . . . . . 135
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 145
Document Revision History . . . . . . . . . . . . . . . . . . 148
This section provides a high-level overview of the device
features. The following figure shows the major functional
units within the device.
Although this document is written from the perspective of
the MPC8548E, most of the material applies to the other
family members, such as MPC8547E, MPC8545E, and
MPC8543E. When specific differences occur, such as pinout
differences and processor frequency ranges, they are
identified as such.
For specific PVR and SVR numbers, see the
MPC8548E
PowerQUICC III Integrated Host Processor Reference
Manual.
Freescale reserves the right to change the detail specifications as may be required
to permit improvements in the design of its products.
© 2007-2012, 2014 Freescale Semiconductor, Inc. All rights reserved.
Overview
DDR
SDRAM
Flash
SDRAM
GPIO
IRQs
Serial
I
2
C
I
2
C
MII, GMII, TBI,
RTBI, RGMII,
RMII
MII, GMII, TBI,
RTBI, RGMII,
RMII
MII, GMII, TBI,
RTBI, RGMII,
RMII
RTBI, RGMII,
RMII
DDR/DDR2/
Memory Controller
Local Bus Controller
Programmable Interrupt
Controller (PIC)
DUART
I
2
C
Controller
I
2
C
Controller
eTSEC
10/100/1Gb
eTSEC
10/100/1Gb
eTSEC
10/100/1Gb
eTSEC
10/100/1Gb
Security
Engine
XOR
Engine
e500
Coherency
Module
512-Kbyte
L2 Cache/
SRAM
e500 Core
32-Kbyte L1
Instruction
Cache
32-Kbyte
L1 Data
Cache
Core Complex
Bus
Serial RapidIO
or
PCI Express
OceaN
Switch
Fabric
4x RapidIO
x8 PCI Express
32-bit PCI Bus Interface
(If 64-bit not used)
32-bit PCI/
64-bit PCI/PCI-X
Bus Interface
4-Channel DMA
Controller
PCI 32-bit
66 MHz
PCI/PCI-X
133 MHz
Figure 1. Device Block Diagram
1.1
Key Features
The following list provides an overview of the device feature set:
• High-performance 32-bit core built on Power Architecture® technology.
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can
be locked entirely or on a per-line basis, with separate locking for instructions and data.
— Signal-processing engine (SPE) APU (auxiliary processing unit). Provides an extensive
instruction set for vector (64-bit) integer and fractional operations. These instructions use both
the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU.
— Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit)
floating-point instructions that use the 64-bit GPRs.
— 36-bit real addressing
— Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set
for single-precision (32-bit) floating-point instructions.
— Memory management unit (MMU). Especially designed for embedded applications. Supports
4-Kbyte to 4-Gbyte page sizes.
— Enhanced hardware and software debug support
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Overview
— Performance monitor facility that is similar to, but separate from, the device performance
monitor
The e500 defines features that are not implemented on this device. It also generally defines some features
that this device implements more specifically. An understanding of these differences can be critical to
ensure proper operations.
•
512-Kbyte L2 cache/SRAM
— Flexible configuration.
— Full ECC support on 64-bit boundary in both cache and SRAM modes
— Cache mode supports instruction caching, data caching, or both.
— External masters can force data to be allocated into the cache through programmed memory
ranges or special transaction types (stashing).
— 1, 2, or 4 ways can be configured for stashing only.
— Eight-way set-associative cache organization (32-byte cache lines)
— Supports locking entire cache or selected lines. Individual line locks are set and cleared through
Book E instructions or by externally mastered transactions.
— Global locking and Flash clearing done through writes to L2 configuration registers
— Instruction and data locks can be Flash cleared separately.
— SRAM features include the following:
– I/O devices access SRAM regions by marking transactions as snoopable (global).
– Regions can reside at any aligned location in the memory map.
– Byte-accessible ECC is protected using read-modify-write transaction accesses for
smaller-than-cache-line accesses.
Address translation and mapping unit (ATMU)
— Eight local access windows define mapping within local 36-bit address space.
— Inbound and outbound ATMUs map to larger external address spaces.
– Three inbound windows plus a configuration window on PCI/PCI-X and PCI Express
– Four inbound windows plus a default window on RapidIO™
– Four outbound windows plus default translation for PCI/PCI-X and PCI Express
– Eight outbound windows plus default translation for RapidIO with segmentation and
sub-segmentation support
DDR/DDR2 memory controller
— Programmable timing supporting DDR and DDR2 SDRAM
— 64-bit data interface
— Four banks of memory supported, each up to 4 Gbytes, to a maximum of 16 Gbytes
— DRAM chip configurations from 64 Mbits to 4 Gbits with ×8/×16 data ports
— Full ECC support
— Page mode support
– Up to 16 simultaneous open pages for DDR
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•
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Overview
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– Up to 32 simultaneous open pages for DDR2
— Contiguous or discontiguous memory mapping
— Read-modify-write support for RapidIO atomic increment, decrement, set, and clear
transactions
— Sleep mode support for self-refresh SDRAM
— On-die termination support when using DDR2
— Supports auto refreshing
— On-the-fly power management using CKE signal
— Registered DIMM support
— Fast memory access via JTAG port
— 2.5-V SSTL_2 compatible I/O (1.8-V SSTL_1.8 for DDR2)
— Support for battery-backed main memory
Programmable interrupt controller (PIC)
— Programming model is compliant with the OpenPIC architecture.
— Supports 16 programmable interrupt and processor task priority levels
— Supports 12 discrete external interrupts
— Supports 4 message interrupts with 32-bit messages
— Supports connection of an external interrupt controller such as the 8259 programmable
interrupt controller
— Four global high-resolution timers/counters that can generate interrupts
— Supports a variety of other internal interrupt sources
— Supports fully nested interrupt delivery
— Interrupts can be routed to external pin for external processing.
— Interrupts can be routed to the e500 core’s standard or critical interrupt inputs.
— Interrupt summary registers allow fast identification of interrupt source.
Integrated security engine (SEC) optimized to process all the algorithms associated with IPSec,
IKE, WTLS/WAP, SSL/TLS, and 3GPP
— Four crypto-channels, each supporting multi-command descriptor chains
– Dynamic assignment of crypto-execution units via an integrated controller
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
— PKEU—public key execution unit
– RSA and Diffie-Hellman; programmable field size up to 2048 bits
– Elliptic curve cryptography with F
2
m and F(p) modes and programmable field size up to
511 bits
— DEU—Data Encryption Standard execution unit
– DES, 3DES
– Two key (K1, K2) or three key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
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Overview
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— AESU—Advanced Encryption Standard unit
– Implements the Rijndael symmetric key cipher
– ECB, CBC, CTR, and CCM modes
– 128-, 192-, and 256-bit key lengths
— AFEU—ARC four execution unit
– Implements a stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
— MDEU—message digest execution unit
– SHA with 160- or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
— KEU—Kasumi execution unit
– Implements F8 algorithm for encryption and F9 algorithm for integrity checking
– Also supports A5/3 and GEA-3 algorithms
— RNG—random number generator
— XOR engine for parity checking in RAID storage applications
Dual I
2
C controllers
— Two-wire interface
— Multiple master support
— Master or slave I
2
C mode support
— On-chip digital filtering rejects spikes on the bus
Boot sequencer
— Optionally loads configuration data from serial ROM at reset via the I
2
C interface
— Can be used to initialize configuration registers and/or memory
— Supports extended I
2
C addressing mode
— Data integrity checked with preamble signature and CRC
DUART
— Two 4-wire interfaces (SIN, SOUT, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D
Local bus controller (LBC)
— Multiplexed 32-bit address and data bus operating at up to 133 MHz
— Eight chip selects support eight external slaves
— Up to eight-beat burst transfers
— The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller.
— Three protocol engines available on a per chip select basis:
– General-purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
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